Field of the Invention
This invention relates to NMOS semiconductor memories, and more particularly to content-addressable memory (CAM) cells.
Most memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory accesses. The time required finding an item stored in memory can be reduced considerably if the item can be identified for access by its content rather than by its address. A memory that is accessed in this way is called content-addressable memory or CAM. CAM provides a performance advantage over other memory search algorithms, such as binary or tree-based searches, by comparing the desired information against the entire list of pre-stored entries simultaneously, often resulting in an order-of-magnitude reduction in the search time.
CAM is ideally suited for several functions, including Ethernet address lookup, data compression, pattern-recognition, cache tags, high-bandwidth address filtering, and fast lookup of routing, user privilege, security or encryption information on a packet-by-packet basis for high-performance data switches, firewalls, bridges and routers.
Since CAM is an outgrowth of Random Access Memory (RAM) technology, in order to understand CAM, it helps to contrast it with RAM. A RAM is an integrated circuit that stores data temporarily. Data is stored in a RAM at a particular location, called an address. In a RAM, the user supplies the address, and gets back the data. The number of address line limits the depth of a memory using RAM, but the width of the memory can be extended as far as desired. With CAM, the user supplies the data and gets back the address. The CAM searches through the memory in one clock cycle and returns the address where the data is found. The CAM can be preloaded at device startup and also be rewritten during device operation. Because the CAM does not need address lines to find data, the depth of a memory system using CAM can be extended as far as desired, but the width is limited by the physical size of the memory.
CAM can be used to accelerate any application requiring fast searches of data-base, lists, or patterns, such as in image or voice recognition, or computer and communication designs. For this reason, CAM is used in applications where search time is very critical and must be very short. For example, the search key could be the IP address of a network user, and the associated information could be user""s access privileges and his location on the network. If the search key presented to the CAM is present in the CAM""s table, the CAM indicates a xe2x80x98matchxe2x80x99 and returns the associated information, which is the user""s privilege. A CAM can thus operate as a data-parallel or Single Instruction/Multiple Data (SIMD) processor.
CAM can be used to accelerate any applications ranging from local-area networks, database management, file-storage management, pattern recognition, artificial intelligence, fully associative and processor-specific cache memories, and disk cache memories. Although CAM has many applications, it is particularly well suited to perform any kind of search operations.
Each CAM cell is essentially a RAM cell with a match function. Match functions can be implemented by adding an exclusive-OR (XOR) or inverse XOR gate to each RAM cell. The XOR output is applied to a match line that connects many CAM cells together in a row or column. The match signal can then be output from the memory.
CAM cells were originally constructed from static RAM (SRAM) cells by adding transistors to perform the XOR function. More recently, CAM cells have also been constructed from dynamic RAM (DRAM) cells. DRAM cells have an area and cost advantage over SRAM cells since a small capacitor stores charge rather than a bi-stable or cross-coupled pair of transistors.
FIG. 1 shows a prior-art dynamic CAM cell using six transistors. U.S. Pat. No. 5,428,564 by Winters shows a six-transistor (6T) CAM cell based on earlier dynamic CAM cells of just 4 or 5 transistors. While the earlier 4T and 5T CAM cells were small in area, these cells were particularly noise sensitive and slow, having relatively low voltage ratios. Winter""s CAM cell uses only n-channel (NMOS) transistors, and has a small area. However, bit-line capacitance is high, the high bit-line capacitance slows read and write operations.
FIG. 2 is a conventional dynamic CAM cell using CMOS transistors. See U.S. Pat. No. 4,791,606 by Threewitt et al. A single bit of data is stored on capacitor when pass transistor is activated by word line WL. Only one bit line BL is used. While such a CMOS CAM cell is useful, integrating p-channel transistors into each cell is expensive. The spacing from a p-channel transistor to an n-channel transistor is large, since separate P and N wells must be made. The spacing between two n-channel transistors is much smaller. Thus the size of the cell is larger when p-channel transistors are included with the r-channel transistors. Also, a single bit line makes reading and writing slow since an absolute voltage rather than a voltage difference is sensed or driven.
What is desired is a CAM cell using only n-channel transistors or p-channel transistors. It is desired to use dynamic storage rather than static storage to reduce the size of the CAM cell.
The invention provides NAND or NOR content-addressable memory (CAM) cells, which selectively use single port, tow ports, or three ports for operations depending on design requirements. These NAND or NOR CAM cells are designed by only n-channel transistors or p-channel transistors. In such designs, one-port bit line with one-port word line, or one-port bit line with two-port word lines, or two-port bit lines with two-port word lines are provided for meeting different purposes.
One arrangement with two-port word lines can be one port word line for refresh and other port word line for SRAM write operation. One of the other arrangements with two-port word lines can be one port word line for read operation and other port word line for write operation, while a wave-pipeline technique is used for refresh cycle (which means hidden refresh). One of the other arrangements with two-port word lines can be one port word line for read operation and other port word line for write operation, while idle a refresh cycle for such dynamic CAM cell.
One arrangement with two-port bit lines can be a match operation and a read/write operation can be performed in the same cycle, while a wave-pipeline technique is used for refresh cycle (which means a hidden refresh method). One of the other arrangements with two-port bit lines is a match operation and a read/write operation can be performed in the same cycle, while idle one cycle for refresh. One of the other arrangements with two-port bit lines is and two-port word line can be one word-line port for refresh and the other word-line port for a SRAM write operation, while the match operation can be performed in the same cycle. One of the other arrangements with two-port bit lines is and two-port word line can be one word-line port for read operation and the other word-line port for write operation, while a wave-pipeline technique for hidden refresh is used for a refresh cycle (which means hidden refresh) and the match operation can be performed in the same cycle. One of the other arrangements with two-port bit lines is and two-port word line can be one word-line port for read operation and the other word-line port for write operation, while the match operation is performed in the same cycle and idle a refresh cycle for refresh operation (for dynamic CAM cells). Such 3-port dynamic differential CAM cells can be implemented by any CMOS technologies, such as FRAM, DRAM, logic technology, etc. These CAM cells can be combined and modified in accordance with different purposes.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor, during the accessing operation mode; a first storage transistor and a first capacitor, a gate of the first storage transistor and the first capacitor for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode; a second storage transistor and a second capacitor, a gate of the second storage transistor and the second capacitor for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode; a match line; a match unit, coupled to the first bit line, the second bit line, the first storage transistor and the second storage transistor. During the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the second bit line receiving a comparing data bit and the first bit line receiving a complement of the comparing data bit, if the complement of the comparing data bit from the first bit line is not logically equal to the storage data bit, or if the comparing data bit from the second bit line is not logically equal to the complement of the storage data bit, the match unit discharging current from the match line to indicate a mis-match signal.
The match unit comprises a first transistor, being coupled a gate the first storage transistor and the first capacitor, a gate of the first transistor being controlled by the storage data bit stored in the a gate the first storage transistor and the first capacitor, a source/drain region of the first transistor being coupled to ground; a second transistor, being coupled a gate of the second storage transistor and the second capacitor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the gate of the second storage transistor and the second capacitor, a source/drain region of the second transistor being coupled to ground; a first match transistor, a gate of the first match transistor being coupled to the first bit line, a source/drain region of the first match transistor being coupled to another ungrounded source/drain region of the first transistor and another source/drain region of the first match transistor being coupled to the match line; and a second match transistor, a gate of the second match transistor being coupled to the second bit line, a source/drain region of the second match transistor being coupled to another ungrounded source/drain region of the second transistor and another source/drain region of the second match transistor being coupled to the match line.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, further comprises a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first storage transistor and the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second storage transistor and the second capacitor, wherein the storage data bit stored in the gate of the first storage transistor and the first capacitor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second storage transistor and the second capacitor being selectively updated in response to the complement of the second data bit.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor, during the accessing operation mode; a first storage transistor, having a first gate for dynamically storing a storage data bit of the memory cell in response to the first data bit; a second storage transistor, having a second gate for dynamically storing a complement of the storage data bit of the memory cell in response to the complement of the first data bit; a match line; and a match unit, coupled to the first bit line, the second bit line, the gate of the first storage transistor and the gate of the second storage transistor. During the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the second bit line receiving a comparing data bit and the first bit line receiving a complement of the comparing data bit, if the complement of the comparing data bit from the first bit line is not logically equal to the storage data bit, or if the comparing data bit from the second bit line is not logically equal to the complement of the storage data bit, the match unit discharging current from the match line to indicate a mis-match signal.
The match unit above-described comprises a first transistor, being coupled the first storage transistor, a gate of the first transistor being controlled by the storage data bit stored in the gate of the first storage transistor, a source/drain region of the first transistor being coupled to ground; a second transistor, being coupled the second storage transistor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the gate of the second storage transistor, a source/drain region of the second transistor being coupled to ground; a first match transistor, a gate of the first match transistor being coupled to the first bit line, a source/drain region of the first match transistor being coupled to another ungrounded source/drain region of the first transistor and another source/drain region of the first match transistor being coupled to the match line; and a second match transistor, a gate of the second match transistor being coupled to the second bit line, a source/drain region of the second match transistor being coupled to another ungrounded source/drain region of the second transistor and another source/drain region of the second match transistor being coupled to the match line.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first storage transistor and the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second storage transistor and the second capacitor, and wherein the storage data bit stored in the gate of the first storage transistor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second storage transistor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first match transistor word line, for connecting the first bit line to the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first match transistor word line, for connecting the second bit line to the second capacitor, during the accessing operation mode; a first capacitor, for storing a storage data bit of the memory cell in response to the first data bit; a second capacitor, for dynamically storing a complement of the storage data bit of the memory cell in response to the complement of the first data bit; a match line; and a match unit, coupled to the first bit line, the second bit line, the first capacitor and the second capacitor. During the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the second bit line receiving a comparing data bit and the first bit line receiving a complement of the comparing data bit, if the complement of the comparing data bit from the first bit line is not logically equal to the storage data bit, or if the comparing data bit from the second bit line is not logically equal to the complement of the storage data bit, the match unit discharging current from the match line to indicate a mis-match signal.
In the above-described memory cell, the match unit comprising: a first transistor, having a gate being controlled by the storage data bit stored in the first capacitor, a source/drain region of the first transistor being coupled to ground; a second transistor, having a gate being controlled by the complement of the storage data bit stored in the second capacitor, a source/drain region of the second transistor being coupled to ground; a first match transistor, a gate of the first match transistor being coupled to the first bit line, a source/drain region of the first match transistor being coupled to another ungrounded source/drain region of the first transistor and another source/drain region of the first match transistor being coupled to the match line; and a second match transistor, a gate of the second match transistor being coupled to the second bit line, a source/drain region of the second match transistor being coupled to another ungrounded source/drain region of the second transistor and another source/drain region of the second match transistor being coupled to the match line.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all p-channel metal-oxide-semiconductor (PMOS) transistors.
The first capacitor and the second capacitor can be MOS capacitors, metal-insulator-metal (MIM) capacitors, polysilicon capacitors, ferroelectric capacitors suitable usage for ferroelectric random-access memory (FRAM), capacitors manufactured by a DRAM process, or magnetoresistive random access memory (MRAM) capacitors made of magnetic materials to store data.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the second capacitor. The storage data bit stored in the first capacitor being selectively updated in response to the second data bit, the storage data bit stored in the second capacitor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all p-channel metal-oxide-semiconductor (PMOS) transistors.
As embodied and broadly described herein, the invention provides a memory cell, comprising: a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first match transistor word line, for connecting the first bit line to the gate of the first transistor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first match transistor word line, for connecting the second bit line to the gate of the second transistor, during the accessing operation mode; a first transistor, having a gate for dynamically storing a storage data bit of the memory cell and having a source/drain region coupling to ground; a second transistor, having a gate for dynamically storing a complement of the storage data bit of the memory cell and having a source/drain region coupling to ground; a match line; a first match transistor, having a gate coupled to the first bit line, a source/drain region being coupled to another ungrounded source/drain region of the first transistor, and another source/drain region being coupled to the match line; and a second match transistor, having a gate being coupled to the second bit line, a source/drain region being coupled to another ungrounded source/drain region of the second transistor, and another source/drain region being coupled to the match line. During the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the second bit line receiving a comparing data bit and the first bit line receiving a complement of the comparing data bit, if the complement of the comparing data bit is not logically equal to the storage data bit, the first match transistor discharging current from the match line to indicate a mis-match signal, if the complement of the comparing data bit from the first bit line is not logically equal to the storage data bit, or if the comparing data bit from the second bit line is not logically equal to the complement of the storage data bit, the second match transistor discharging current from the match line to indicate a mis-match signal.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all p-channel metal-oxide-semiconductor (PMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the second capacitor. The storage data bit stored in the gate of the first transistor is selectively updated in response to the second data bit, and the storage data bit stored in the gate of the second transistor is selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all p-channel metal-oxide-semiconductor (PMOS) transistors.
As embodied and broadly described herein, the invention provides a memory cell, comprising: a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for controlling data transmitting between the first and second bit lines and the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor; a first storage transistor and a first capacitor, a gate of the first storage transistor and the first capacitor for dynamically storing a storage data bit of the memory cell in response to the first data bit; a second storage transistor and a second capacitor, a gate of the second storage transistor and the second capacitor for dynamically storing a complement of the storage data bit of the memory cell in response to complement of the first data bit; a first compare line, for transmitting a compare data bit to the memory cell; a second compare bit line, for transmitting a complement of the compare data bit to the memory cell; a match line; and a match unit, coupled to the first and second bit lines, the first and second compare lines, the first storage transistor and the second storage transistor. During comparison operation of the memory cell, the compare data bit being conducted to the first and second compare lines, and if the complement of the comparing data bit from the first compare line is not logically equal to the storage data bit, or if the comparing data bit from the second compare line is not logically equal to the complement of the storage data bit, the match unit discharging current from the match line to indicate a mis-match signal.
In the above-described memory cell, the match unit comprises a first transistor, being coupled to a gate of the first storage transistor and the first capacitor, a gate of the first transistor being controlled by the storage data bit stored in the first storage transistor and the first capacitor, a source/drain region of the first transistor being coupled to ground; a second transistor, being coupled to a gate of the second storage transistor and the second capacitor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the second storage transistor and the second capacitor, a source/drain region of the second transistor being coupled to ground; a first match transistor, a gate of the first match transistor being controlled by the first compare line, a source/drain region of the first match transistor being coupled to another ungrounded source/drain region of the first transistor and another source/drain region of the first match transistor being coupled to the match line; and a second match transistor, a gate of the second match transistor being controlled by the second compare line, a source/drain region of the second match transistor being coupled to another ungrounded source/drain region of the second transistor and another source/drain region of the second match transistor being coupled to the match line.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, further comprises a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first storage transistor and the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second storage transistor and the second capacitor. The storage data bit stored in the gate of the first storage transistor and the first capacitor is selectively updated in response to the second data bit, and the storage data bit stored in the gate of the second storage transistor and the second capacitor is selectively updated in response to the complement of the second data bit.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for controlling data transmitting between the first and second bit lines and the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor; a first storage transistor, having a gate for dynamically storing a storage data bit of the memory cell in response to the first data bit; a second storage transistor, having a gate for dynamically storing a complement of the storage data bit of the memory cell in response to complement of the first data bit; a first compare line, for transmitting a compare data bit to the memory cell; a second compare bit line, for transmitting a complement of the compare data bit to the memory cell; a match line; and a match unit, coupled to the first and second bit lines, the first and second compare lines, the first storage transistor and the second storage transistor. During comparison operation of the memory cell, the compare data bit is conducted to the first and second compare lines, and if the complement of the comparing data bit from the first compare line is not logically equal to the storage data bit, or if the comparing data bit from the second compare line is not logically equal to the complement of the storage data bit, the match unit discharges current from the match line to indicate a mis-match signal.
In the above-described memory cell, the match unit comprising: a first transistor, being coupled to a gate of the first storage transistor and the first capacitor, a gate of the first transistor being controlled by the storage data bit stored in the first storage transistor, a source/drain region of the first transistor being coupled to ground; a second transistor, being coupled to a gate of the second storage transistor and the second capacitor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the second storage transistor, a source/drain region of the second transistor being coupled to ground; a first match transistor, a gate of the first match transistor being controlled by the first compare line, a source/drain region of the first match transistor being coupled to another ungrounded source/drain region of the first transistor and another source/drain region of the first match transistor being coupled to the match line; and a second match transistor, a gate of the second match transistor being controlled by the second compare line, a source/drain region of the second match transistor being coupled to another ungrounded source/drain region of the second transistor and another source/drain region of the second match transistor being coupled to the match line.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell, a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first storage transistor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second storage transistor, the storage data bit stored in the gate of the first storage transistor and the first capacitor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second storage transistor and the second capacitor being selectively updated in response to the complement of the second data bit.
As embodied and broadly described herein, the invention provides a memory cell, comprising: a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for controlling data transmitting between the first and second bit lines and the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the first capacitor; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the second capacitor; a first capacitor, for dynamically storing a storage data bit of the memory cell in response to the first data bit; a second capacitor, for dynamically storing a complement of the storage data bit of the memory cell in response to complement of the first data bit; a first compare line, for transmitting a compare data bit to the memory cell; a second compare bit line, for transmitting a complement of the compare data bit to the memory cell; a match line; and a match unit, coupled to the first and second bit lines, the first and second compare lines, the first storage transistor and the second storage transistor. During comparison operation of the memory cell, the compare data bit being conducted to the first and second compare lines, and if the complement of the comparing data bit from the first compare line is not logically equal to the storage data bit, or if the comparing data bit from the second compare line is not logically equal to the complement of the storage data bit, the match unit discharging current from the match line to indicate a mis-match signal.
In the above-described memory cell, the match unit comprising: a first transistor, being coupled to the first capacitor, a gate of the first transistor being controlled by the storage data bit stored in the first capacitor, a source/drain region of the first transistor being coupled to ground; a second transistor, being coupled to the second capacitor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the second capacitor, a source/drain region of the second transistor being coupled to ground; a first match transistor, a gate of the first match transistor being controlled by the first compare line, a source/drain region of the first match transistor being coupled to another ungrounded source/drain region of the first transistor and another source/drain region of the first match transistor being coupled to the match line; and a second match transistor, a gate of the second match transistor being controlled by the second compare line, a source/drain region of the second match transistor being coupled to another ungrounded source/drain region of the second transistor and another source/drain region of the second match transistor being coupled to the match line.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors or p-channel metal-oxide-semiconductor (PMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the second capacitor, wherein the storage data bit stored in the gate of the first storage transistor and the first capacitor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second storage transistor and the second capacitor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors, or p-channel metal-oxide-semiconductor (PMOS) transistors.
In the above-described memory cell, the first capacitor and the second capacitor are metal-insulator-metal (MIM) capacitors, polysilicon capacitors, ferroelectric random-access memory (FRAM), capacitors manufactured by a DRAM process, or magnetoresistive random access memory (MRAM) capacitors made of magnetic materials to store data.
As embodied and broadly described herein, the invention provides a memory cell, comprising: a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for controlling data transmitting between the first and second bit lines and the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first transistor; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second transistor; a first transistor, having a gate for dynamically storing a storage data bit of the memory cell in response to the first data bit and having a source/drain region coupling to ground; a second transistor, having a gate for dynamically storing a complement of the storage data bit of the memory cell in response to the complement of the first data bit and having a source/drain region coupling to ground; a first compare line, for transmitting a compare data bit to the memory cell; a second bit line, for transmitting a complement of the compare data bit to the memory cell; a match line; a first match transistor, having a gate coupled to the first compare line, a source/drain region being coupled to another ungrounded source/drain region of the first transistor, and another source/drain region being coupled to the match line; and a second match transistor, having a gate being coupled to the second compare line, a source/drain region being coupled to another ungrounded source/drain region of the second transistor, and another source/drain region being coupled to the match line, wherein during comparison operation of the memory cell, the compare data bit being conducted to the first and second compare lines, and if the complement of the comparing data bit from the first compare line is not logically equal to the storage data bit, or if the comparing data bit from the second compare line is not logically equal to the complement of the storage data bit, the match unit discharging current from the match line to indicate a mis-match signal.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors or PMOS transistors
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first transistor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second transistor, wherein the storage data bit stored in the gate of the first transistor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second transistor being selectively updated in response to the complement of the second data bit.
As embodied and broadly described herein, the invention provides a memory cell, comprising a memory cell, comprising: a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor, during the accessing operation mode; a first storage transistor and a first capacitor, a gate of the first storage transistor and the first capacitor for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode; a second storage transistor and a second capacitor, a gate of the second storage transistor and the second capacitor for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode; a first transistor, being coupled to a gate the first storage transistor and the first capacitor, a gate of the first transistor being controlled by the storage data bit stored in the a gate the first storage transistor and the first capacitor, a source/drain region of the first transistor being coupled to the first bit line; a second transistor, being coupled to a gate of the second storage transistor and the second capacitor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the gate of the second storage transistor and the second capacitor, a source/drain region of the second transistor being coupled to the second bit line; and a match transistor, having a gate coupled to an unconnected source/drain region of the first transistor and an unconnected source/drain region of the second transistor, wherein during the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the first bit line receiving a comparing data bit and the second bit line receiving a complement of the comparing data bit, if the comparing data bit from the first bit line is logically equal to the storage data bit, or if the comparing data bit from the second bit line is logically equal to the complement of the storage data bit, the match transistor being turned on to indicate a match signal.
In the above-described memory cell, the first and second pass transistors, the first and second transistors, and the match transistor are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first transistor and the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second transistor and the second capacitor, wherein the storage data bit stored in the gate of the first transistor and the first capacitor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second transistor and the second capacitor being selectively updated in response to the complement of the second data bit.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor, during the accessing operation mode; a first capacitor, for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode; a second capacitor, for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode; a first transistor, being coupled to the first capacitor, a gate of the first transistor being controlled by the storage data bit stored in the first capacitor, a source/drain region of the first transistor being coupled to the first bit line; a second transistor, being coupled to the second capacitor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the second capacitor, a source/drain region of the second transistor being coupled to the second bit line; and a match transistor, having a gate coupled to an unconnected source/drain region of the first transistor and an unconnected source/drain region of the second transistor, during the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the first bit line receiving a comparing data bit and the second bit line receiving a complement of the comparing data bit, if the comparing data bit from the first bit line is logically equal to the storage data bit, or if the comparing data bit from the second bit line is logically equal to the complement of the storage data bit, the match transistor being turned on to indicate a match signal.
In the above-described memory cell, the first and second pass transistors, the match transistor, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors, or p-channel metal-oxide-semiconductor (PMOS) transistors.
In the above-described memory cell, the first and second pass transistors, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first transistor and the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second transistor and the second capacitor, wherein the storage data bit stored in the gate of the first transistor and the first capacitor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second transistor and the second capacitor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the first and second pass transistors, the third and forth pass transistors, the match transistor, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors, or all p-channel metal-oxide-semiconductor (PMOS) transistors
The first capacitor and the second capacitor are metal-insulator-metal (MIM) capacitors, polysilicon capacitors, ferroelectric capacitors suitable usage for ferroelectric random-access memory (FRAM), capacitors manufactured by a DRAM process, or magnetoresistive random access memory (MRAM) capacitors made of magnetic materials to store data.
As embodied and broadly described herein, the invention provides a memory cell, comprising a memory cell a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor, during the accessing operation mode; a first storage transistor, having a gate for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode; a second storage transistor, having a gate for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode; a first transistor, being coupled to a gate the first storage transistor, a gate of the first transistor being controlled by the storage data bit stored in the a gate the first storage transistor, a source/drain region of the first transistor being coupled to the first bit line; a second transistor, being coupled to a gate of the second storage transistor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the gate of the second storage transistor, a source/drain region of the second transistor being coupled to the second bit line; and a match transistor, having a gate coupled to an unconnected source/drain region of the first transistor and an unconnected source/drain region of the second transistor, during the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the first bit line receiving a comparing data bit and the second bit line receiving a complement of the comparing data bit, if the comparing data bit from the first bit line is logically equal to the storage data bit, or if the comparing data bit from the second bit line is logically equal to the complement of the storage data bit, the match transistor being turned on to indicate a match signal.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second transistors, and the match transistor are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first storage transistor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second storage transistor, wherein the storage data bit stored in the gate of the first storage transistor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second storage transistor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the first and second match transistors, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first transistor, having a gate for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode, a source/drain region of the first transistor being coupled to the first bit line; a second transistor, having a gate for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode, a source/drain region of the second transistor being coupled to the second bit line; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first transistor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second transistor, during the accessing operation mode; a match transistor, having a gate coupled to an unconnected source/drain region of the first transistor and an unconnected source/drain region of the second transistor, during the comparison operation mode of the memory cell, the first word line stopping data transmitting between the first and second bit lines and the memory cell, the first bit line receiving a comparing data bit and the second bit line receiving a complement of the comparing data bit, if the comparing data bit from the first bit line is logically equal to the storage data bit, or if the comparing data bit from the second bit line is logically equal to the complement of the storage data bit, the match transistor being turned on to indicate a match signal.
In the above-described memory cell, the first and second pass transistors, the first and second transistors, and the match transistor are all n-channel metal-oxide-semiconductor (NMOS) transistors, or all p-channel metal-oxide-semiconductor (PMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first transistor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second transistor, wherein the storage data bit stored in the gate of the first transistor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second transistor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the match transistor, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors, or all p-channel metal-oxide-semiconductor (PMOS) transistors.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor, during the accessing operation mode; a first storage transistor and a first capacitor, a gate of the first storage transistor and the first capacitor for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode; a second storage transistor and a second capacitor, a gate of the second storage transistor and the second capacitor for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode; a first compare line, for transmitting a compare data bit to the memory cell; a second compare bit line, for transmitting a complement of the compare data bit to the memory cell; a first transistor, being coupled to a gate the first storage transistor and the first capacitor, a gate of the first transistor being controlled by the storage data bit stored in the a gate the first storage transistor and the first capacitor, a source/drain region of the first transistor being coupled to the first compare line; a second transistor, being coupled to a gate of the second storage transistor and the second capacitor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the gate of the second storage transistor and the second capacitor, a source/drain region of the second transistor being coupled to the second compare line; and a match transistor, having a gate coupled to an unconnected source/drain region of the first transistor and an unconnected source/drain region of the second transistor, during the comparison operation mode of the memory cell, the first compare line receiving a comparing data bit and the second compare line receiving a complement of the comparing data bit, if the comparing data bit from the first compare line is logically equal to the storage data bit, or if the comparing data bit from the second compare line is logically equal to the complement of the storage data bit, the match transistor being turned on to indicate a match signal.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second transistors, and the match transistor are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first storage transistor and the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second storage transistor and the second capacitor, wherein the storage data bit stored in the gate of the first transistor and the first capacitor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second transistor and the second capacitor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the match transistor, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor, during the accessing operation mode; a first storage transistor, having a gate for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode; a second storage transistor, having a gate for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode; a first compare line, for transmitting a compare data bit to the memory cell; a second compare bit line, for transmitting a complement of the compare data bit to the memory cell; a first transistor, being coupled to a gate the first storage transistor, a gate of the first transistor being controlled by the storage data bit stored in the a gate the first storage transistor, a source/drain region of the first transistor being coupled to the first compare line; a second transistor, being coupled to a gate of the second storage transistor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the gate of the second storage transistor, a source/drain region of the second transistor being coupled to the second compare line; and a match transistor, having a gate coupled to an unconnected source/drain region of the first transistor and an unconnected source/drain region of the second transistor, during the comparison operation mode of the memory cell, the first compare line receiving a comparing data bit and the second compare line receiving a complement of the comparing data bit, if the comparing data bit from the first compare line is logically equal to the storage data bit, or if the comparing data bit from the second compare line is logically equal to the complement of the storage data bit, the match transistor being turned on to indicate a match signal.
In the above-described memory cell, the first and second pass transistors, the first and second storage transistors, the first and second transistors, and the match transistor are all n-channel metal-oxide-semiconductor (NMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first transistor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second transistor and the second capacitor, wherein the storage data bit stored in the gate of the first storage transistor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second storage transistor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the first and second storage transistors, the match transistor, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor, during the accessing operation mode; a first capacitor, for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode; a second capacitor, for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode; a first compare line, for transmitting a compare data bit to the memory cell; a second compare bit line, for transmitting a complement of the compare data bit to the memory cell; a first transistor, being coupled to the first capacitor, a gate of the first transistor being controlled by the storage data bit stored in the first capacitor, a source/drain region of the first transistor being coupled to the first compare line; a second transistor, being coupled to the second capacitor, a gate of the second transistor being controlled by the complement of the storage data bit stored in the gate of the second capacitor, a source/drain region of the second transistor being coupled to the second compare line; and a match transistor, having a gate coupled to an unconnected source/drain region of the first transistor and an unconnected source/drain region of the second transistor, during the comparison operation mode of the memory cell, the first compare line receiving a comparing data bit and the second compare line receiving a complement of the comparing data bit, if the comparing data bit from the first compare line is logically equal to the storage data bit, or if the comparing data bit from the second compare line is logically equal to the complement of the storage data bit, the match transistor being turned on to indicate a match signal.
In the above-described memory cell, the first and second pass transistors, the first and second transistors, and the match transistor are all n-channel metal-oxide-semiconductor (NMOS) transistors, or all p-channel metal-oxide-semiconductor (PMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the first capacitor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the second capacitor, wherein the storage data bit stored in the first capacitor being selectively updated in response to the second data bit, the storage data bit stored in the second capacitor being selectively updated in response to the complement of the second data bit.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the match transistor, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors, or p-channel metal-oxide-semiconductor (PMOS) transistors.
In the above-described memory cell, the first capacitor and the second capacitor are metal-insulator-metal (MIM) capacitors, polysilicon capacitors, ferroelectric capacitors suitable usage for ferroelectric random-access memory (FRAM), capacitors manufactured by a DRAM process, or magnetoresistive random access memory (MRAM) capacitors made of magnetic materials to store data.
As embodied and broadly described herein, the invention provides a memory cell, comprising a first bit line, for transmitting a first data bit to the memory cell; a second bit line, for transmitting a complement of the first data bit to the memory cell; a first word line, for selectively controlling data transmitting between the first and second bit lines and the memory cell in accordance with an accessing operation mode and a comparison operation mode of the memory cell; a first pass transistor, having a gate controlled by the first word line, for connecting the first bit line to the gate of the first storage transistor and the first capacitor, during the accessing operation mode; a second pass transistor, having a gate controlled by the first word line, for connecting the second bit line to the gate of the second storage transistor and the second capacitor, during the accessing operation mode; a first compare line, for transmitting a compare data bit to the memory cell; a second compare bit line, for transmitting a complement of the compare data bit to the memory cell; a first transistor, having a gate for dynamically storing a storage data bit of the memory cell in respond to the first data bit during the accessing operation mode, a source/drain region of the first transistor being coupled to the first compare line; a second transistor, having a gate for dynamically storing a complement of the storage data bit of the memory cell in respond to the complement of first data bit during the accessing operation mode, a source/drain region of the second transistor being coupled to the first compare line; and a match transistor, having a gate coupled to an unconnected source/drain region of the first transistor and an unconnected source/drain region of the second transistor, during the comparison operation mode of the memory cell, the first compare line receiving a comparing data bit and the second compare line receiving a complement of the comparing data bit, if the comparing data bit from the first compare line is logically equal to the storage data bit, or if the comparing data bit from the second compare line is logically equal to the complement of the storage data bit, the match transistor being turned on to indicate a match signal.
In the above-described memory cell, the first and second pass transistors, the first and second transistors, and the match transistor are all n-channel metal-oxide-semiconductor (NMOS) transistors, or all p-channel metal-oxide-semiconductor (PMOS) transistors.
In the above-described memory cell, further comprising a third bit line, for transmitting a second data bit to the memory cell; a forth bit line, for transmitting a complement of the second data bit to the memory cell; a second word line, for selectively controlling data transmitting between the third and forth bit lines and the memory cell in accordance with the accessing operation mode and the comparison operation mode of the memory cell; a third pass transistor, having a gate controlled by the second word line, for connecting the third bit line to the gate of the first transistor; and a forth pass transistor, having a gate controlled by the second word line, for connecting the forth bit line to the gate of the second transistor, wherein the storage data bit stored in the gate of the first transistor being selectively updated in response to the second data bit, the storage data bit stored in the gate of the second transistor being selectively updated in response to the complement of the second data bit.
As embodied and broadly described herein, the invention provides a simple peripheral circuit with CAM cells describe above for one word comparison operation. In such arrangement, the number of CAM cells is dependent on the bit number of the one-word comparison; for example, n bits being compared simultaneously and a match signal being signaled after comparison. The CAM cells can be one of all types of the CAM cells described in the first, second and third preferred embodiments. The match sense line (MSL) is pre-charged high before a compare operation. When the comparing data matches the stored data in the CAM cells, match sense line MSL remains high. When the comparing data matches the stored data in the CAM cells, match sense line MSL remains high. When the comparing data does not match the stored data in the CAM cells, match sense line MSL is pulled low. In such architecture, a n-bit word comparison operation can be easily implemented.
As embodied and broadly described herein, the invention provides a simple peripheral circuit with CAM cells describe above for multiple-word comparison operation. In such arrangement, the number of CAM cells is dependent on the bit number of the word for such comparison; for example, n bits of one word being compared simultaneously and a match signal being signaled after comparison. For multiple words, for example, m words, m rows for n-bit comparison will be arranged for such m-word comparison. The CAM cells can be one of all types of the CAM cells described in the first, second and third preferred embodiments. The match sense line (MSL) is pre-charged high before a compare operation. When the comparing data matches the stored data in the CAM cells, match sense line MSL remains high. When the comparing data matches the stored data in the CAM cells, match sense line MSL remains high. When the comparing data does not match the stored data in the CAM cells, match sense line MSL is pulled low. By using a encoder device, such as encoder ROM, a result signal can be easily signaled for simultaneously comparing m words. The numbers of m and n are determined in accordance with the design requirements.
As embodied and broadly described herein, the invention provides a simple peripheral circuit with CAM cells describe above for one word comparison operation. In such arrangement, the number of CAM cells is dependent on the bit number of the one-word comparison; for example, n bits being compared simultaneously and a match signal being signaled after comparison. The CAM cells can be one of all types of the CAM cells described in the fifth-preferred embodiment. The match transistors MT1, MT2, MT3 . . . MTn are specifically turned on if the comparing data matches the stored data in the CAM cells. If all of the n match transistors are turned on, the current path will be established through the evaluation transistor to the pre-charge transistor. The one-word comparison operation can be easily implemented. For reducing power consumption during comparison operation because too many transistors are turned on simultaneously, another row of n match transistors can be used in the implementation for other n-bit comparison. By simply using a logic AND gate, the Match signal is generated from results of two or more n-bit comparison operations, which are used for the one-word comparison operation with more and more bits.
As embodied and broadly described herein, the invention provides a simple peripheral circuit with CAM cells describe above for multiple-word comparison operation. In such arrangement, the number of CAM cells is dependent on the bit number of the word for such comparison; for example, n bits of one word being compared simultaneously and a Match signal being signaled after comparison. For other example, several n-bit comparison operations can also be performed simultaneously and a Match signal being signaled by using a AND gate.
For multiple words, for example, m words, m rows for n-bit comparisons will be arranged for such m-word comparison. The CAM cells can be one of all types of the CAM cells described in the fifth-preferred embodiments. Match signals such as Matchi, Matchj and Matchk are generated after several n-bit comparison operations. By using a encoder device, such as encoder ROM, a result signal can be easily signaled for simultaneously comparing m words. The numbers of m and n are determined in accordance with the design requirements.
In the above-described memory cell, the first and second pass transistors, the third and forth pass transistors, the match transistor, and the first and second transistors are all n-channel metal-oxide-semiconductor (NMOS) transistors, or all p-channel metal-oxide-semiconductor (PMOS) transistors